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Mobile Fast Charging Circuit: From USB-C PD to Battery Cell Architecture

Modern flagships push 120W through a USB-C connector smaller than your fingernail. Here’s how the power actually gets from the wall to the anode — without melting the PCB.

PCB & Hardware Teardown Sep 02, 2026 • 9 min read • USB-C PD Charge Pump BMS
PN
Priya Nair — Mobile Network Specialist
Hardware systems & power delivery at Jones Consortium • 12 years in mobile PMIC validation

When Xiaomi introduced 210W charging in 2022, many assumed it was a marketing stunt. Three years later, 100W is baseline for Chinese flagships, and even conservative vendors like Samsung and Apple now exceed 45W with PPS. The trick isn’t just a bigger brick — it’s a complete redesign of the charging path from VBUS to the jelly-roll.

We tore down the charging subsystems of six 2025-2026 devices — including split-board flagships using Qualcomm SMB248x and TI BQ25970 families — to map the full chain: PD negotiation, input protection, switched-capacitor conversion, and dual-cell balancing. If you design around PMICs, this is the block you can no longer treat as an afterthought.

1. The USB-C PD Handshake Is Now a Power Negotiation Engine

Gone are the days of 5V/2A D+/D- detection. Every fast-charge path today starts as a USB Power Delivery 3.1 conversation over the CC line. The phone’s TCPM (Type-C Port Manager) — often integrated in the main PMIC or a standalone TCPC like the Richtek RT1718 — advertises its Sink Capabilities, then requests a Source PDO that minimizes conversion loss.

Flagships universally prefer PPS APDO over fixed PDOs. Why? A fixed 10V/6A PDO forces the charger to output exactly 10V. If the battery is at 7.6V (dual-cell ~3.8V each), a 2:1 charge pump wants 15.2V at its input to run at 97% efficiency — not 10V. PPS lets the phone request 7.6V × 2 + headroom = ~15.6V in 20mV steps, and then nudge it 100mV every 200ms as the cell voltage rises.

This tight loop is what connects charging speed to software. As we covered in our mobile app launch speed benchmark, sustained SoC power is gated by thermal headroom — and the charging subsystem is now the biggest transient heat source on the board. A 2°C reduction in converter loss directly buys you longer peak CPU time.

// Captured USB PD trace – 120W PPS device (simplified)
SRC_CAPS: Fixed 5V@3A, 9V@3A, 15V@3A, 20V@6A | APDO 3.3-21V@6A (PPS)
SNK_REQ: APDO 15.6V @ 6.0A (93.6W) | EPR: not requested
BATT STS: 2S1P 7.82V (3.91V/cell), 42°C, JEITA = Normal
PD CTRL: TCPM adjusts every 180ms: +40mV if Ibat < target && Tdie < 43°C
// I2C register pacing: 0x34 (VBUS target) -> TCPC -> CC TX

Protocols like VOOC/SuperVOOC and Xiaomi HyperCharge still use a custom MCU in the adapter for even finer current control, but all now tunnel over PD 3.0 vendor-defined messages to remain compatible with USB-IF certified cables. That convergence matters for PCB design: you must handle 6A over VBUS/GND pins with 40mΩ contact resistance without violating the app store security review process for authentication ICs — many chargers now embed an SHA256 auth chip on CC.

2. The Charging IC: Buck-Boost vs. Charge Pump

Inside the phone, VBUS first hits an OVP/FET array (e.g., TI BQ76200) for 28V surge protection and reverse blocking, then a sense resistor and buck-boost pre-regulator that handles legacy 5V input. The real workhorse for 50W+ is the switched-capacitor charge pump.

Mobile Connectivity Standards Comparison
Feature 5G NR Wi-Fi 7 Bluetooth 5.4
Peak Throughput20 Gbps46 Gbps2 Mbps
Latency1–4 ms1–2 ms3–6 ms
RangeSeveral km30–50 m100–400 m
Power DrawHighMediumUltra-low
Primary UseCellular dataLocal networkingPeripherals/IoT

A classic buck converter steps voltage with an inductor: efficient (~92%) but hot and large at 6A. A 2:1 charge pump uses four FETs and two flying capacitors to halve voltage and double current capacitively — no inductor, 98.2% peak efficiency in the BQ25970 at 4A.

Topology in practice:

Fast Charging Power Path Block Diagram Block diagram from USB-C through charge pump to dual battery cells 120W MOBILE CHARGING POWER PATH (2S DUAL-CELL PPS) USB-C PORT CC + VBUS (6A) TCPC / TCPM OVP + FET 28V Surge / 30mΩ BQ76200 2:1 CHARGE PUMP x2 Switched-Capacitor 97.8% BQ25970 / SMB2482 (parallel) Iin 6A → Iout 12A BMS + BALANCER JEITA / Coulomb BQ27z746 2S Li-Po 3.91V + 3.91V = 7.82V 5000mAh (2x2500) BUCK-BOOST TRICKLE (5V) Legacy / Low-power path 2A VBUS 15.6V@6A → Vbat 7.8V@12A (93W delivered, ~2W loss as heat) Flying caps: 4× 47µF / FETs: 4× 1.8mΩ • NTC per cell + die temp throttling at 43°C I²C / SPMI control by AP + PMIC • PDO update every 150-200ms via PPS
Figure 1 — High-power PPS path (solid) vs. legacy buck path (dashed). Two charge pumps run in parallel for current sharing and thermal spreading.

Most 100W+ phones run two charge pumps in parallel on opposite sides of the motherboard. Each handles ~3A input, which halves hot-spot density and lets copper pours spread heat toward the vapor chamber. A master-slave configuration synchronizes the switching phase 180° apart to cancel ripple at the battery.

Efficiency curves tell the story: at VBAT = 8V, VBUS = 16.2V gives 98.1% efficiency but 15V drops to 96.4% — that 1.7% delta is 1.6W of extra heat at 93W. Hence the PPS micro-steps. Firmware continuously hunts for VBus = 2 × Vbat + 80-120mV overhead.

Design note: Flying capacitors must be 25V X5R with ESR < 5mΩ, placed within 2mm of the FETs. We’ve seen boards fail PPS certification due to 8mm cap traces adding 2nH that creates 3V overshoot on the switching node at 1MHz.

3. Dual-Cell Battery Architecture — Why Series Beats Parallel

Single-cell (1S) batteries cap at 4.45V. To push 100W into a 1S cell you need 22A at the anode — impossible without massive busbars and destructive I²R heating inside the jelly-roll (P = I² × 35mΩ = 17W just in the cell tab). The industry pivot is 2S1P: two 2500mAh cells stacked in series.

In 2S, 100W at 8.8V full charge is ~11.3A. That same power splits as ~5.65A per cell interconnect in a 1S2P parallel configuration, but more importantly, the charge pump input current halves. Cable loss scales quadratically, so halving current quarters loss — enabling standard 5A-rated USB-C e-marker cables to carry 92W.

Series brings complexity: cell balancing. Even with matched cells, capacity variance ±1.5% and impedance mismatch cause one cell to hit 4.45V earlier. A passive balancer bleeds ~80mA via 56Ω resistors, but flagship BMS now use active shuttle balancing or simply throttle the charge pump to CV mode when ΔV > 25mV. TI’s BQ27z746 lineage adds 1mV ADC and coulomb counting with learning cycles to keep State-of-Charge error < 1% — critical because the system must shut off at precisely 8.90V (4.45V/cell).

This is where mobile AI agent on-device workload forecasting starts to matter: the OS predicts the next 10 minutes of power draw and biases the JEITA table. If a heavy inference task is queued, the BMS may briefly hold at 85% and resume topping after the load, keeping the cells cooler than a naive CC-CV.

4. Comparison: Charging Topologies in Shipping Phones

Topology Example IC Peak Efficiency Full Power Cell Config Cable Req.
Single Buck TI BQ25628, SC8981H 93.5% 18–30W 1S1P (4.45V) 3A USB-C
Buck-Boost + PPS Qualcomm SMB1396 95.2% 45–65W 1S1P 3–5A PPS
1× 2:1 Charge Pump TI BQ25970, HL7139 98.1% 67–80W 2S1P (8.8V) 3.3A PPS
2× 2:1 Parallel Pump SMB2482 ×2, BQ25980 ×2 97.8% 100–120W 2S1P 5–6A PPS
4:2 Dual Pump LN8000 ×2 (Samsung) 97.3% 210W 2S1P Proprietary 10A

The table hides a PCB reality: 210W still needs a custom 10A connector with extra VBUS pins and is not USB-IF compliant. The sweet spot for global SKUs is dual 2:1 around 100W — it fits a standard e-marker 5A cable using PPS at 20V, passes IEC thermal tests, and keeps the battery tab delta under 3°C.

5. Thermal, BMS, and Safety Loops

Fast charging is a thermal problem first. The JEITA standard throttles current in three zones: < 15°C (reduce to 0.3C), 15–45°C (full speed), >45°C (taper). Modern phones have 4–5 NTCs: two on the cell tabs, one on the charge pump die, one on the USB connector, and one on the mid-frame near the AP. The BMS polls them at 100ms and can collapse current from 12A to 2A within two PPS intervals.

Safety is multi-layered. Primary protection is the fuel-gauge MOSFETs (secondary protection is a one-time chemical fuse — SCP — that blows at 135°C or 4.6V/cell). The charge pump itself integrates input OVP at 22V, flying-cap short detection, and watchdog: if the AP crashes during charging, the pump shuts down after 1.2s without I2C ack.

We also see growing integration with modem subsystems. The satellite 5G convergence radios demand bursty 5W TX that coincides with charging heat — flagships now sequence non-terrestrial network registration around CV phase, not the CC peak, to avoid stacking thermal loads.

6. PCB Layout Rules That Make or Break 6A

Schematic is 30% of the job; layout is 70%. At 6A DC, a 10mm trace of 1oz copper at 0.5mm width drops 40mV and dissipates 0.24W — enough to lift the local temp 12°C in a 0.8mm board.

Key rules from teardown measurements:

Power and Ground

Use 2oz copper on VBUS/GND layers and keep the loop from USB-C → OVP → pump → battery ≤ 15mm per segment. Pour solid copper under the pump FETs and stitch with 0.3mm vias to an inner GND plane every 1.5mm. Keep flying-cap loops < 3mm perimeter to limit EMI at 1.2MHz switching — we measured 6dB lower radiated emissions when the loop area dropped from 18mm² to 7mm².

Sensing and Control

Kelvin-sense the battery voltage directly at the cell tabs, not at the pump output inductor pad; a 15mΩ trace error reads as 180mV at 12A and can overcharge a cell. Route I2C/SMBus with 22Ω series damping and keep at least 0.8mm clearance from the switching node to avoid coupling.

// Devicetree snippet – dual charge pump on Snapdragon 8 Gen 3 platform
qcom,chg-pump@34 { // BQ25970 @ 0x68 (pump1) & 0x69 (pump2)
  compatible = "ti,bq25970";
  reg = <0x68>; role = "master"; ti,switching-freq = <1200000>;
  ti,ovp-threshold-mv = <22000>; ti,ibus-ocp-ma = <6500>;
  ti,busovp-gate-us = <20>; // fast OVP for PPS spikes
};
qcom,jeita-table {
  temp-limits = <15 450 600>; // 0.3C below 15°C, taper above 45°C
  volt-comp-mv = <0 -50 -100>;
}

Finally, connector choice matters. Standard USB-C is rated 5A continuous, but at 6A the contact can reach 68°C at 25°C ambient. Vendors targeting 120W use “L-shaped” mid-mount connectors with dual VBUS blades and thicker lead-frames, validated to 8A with 15K-cycle durability.

Fast charging has evolved from a standalone block into a system-level negotiation between adapter, cable, thermal headroom, and battery chemistry. Get the charge pump right and you shave eight minutes off a 0–100% cycle; get the sensing wrong and you shave 200 cycles off the battery’s life. The margin between the two is a couple of millivolts and a few square millimeters of copper.

Frequently Asked Questions

Why do phones use charge pumps instead of traditional buck converters for 100W+ charging?
Charge pumps use a switched-capacitor 2:1 topology that halves voltage and doubles current without an inductor. This yields 97–98% efficiency versus ~92% for bucks at 6A, drastically reducing heat and board area. Two pumps in parallel further spread thermal load and cancel ripple when run 180° out of phase.
What is the difference between USB PD PPS and fixed PDO?
Fixed PDO offers only discrete voltages (5V, 9V, 15V, 20V). PPS (Programmable Power Supply) allows fine 20mV steps from 3.3–21V, letting the phone continuously tune VBUS to stay at 2× battery voltage + headroom. This keeps the charge pump at its efficiency peak and prevents thermal throttling.
Why are flagship phones moving to dual-cell batteries?
A 2S battery doubles pack voltage to ~8.8V. For the same wattage, current halves, so I²R losses in the cable and tabs drop by ~75%. A 2:1 charge pump then maps cleanly from ~16–18V at VBUS to ~8V at the pack, enabling 100W over a standard 5A USB-C cable without exotic connectors.
Can fast charging degrade battery health faster?
Not significantly when JEITA, coulomb counting, and adaptive CV are implemented. Dual-cell designs actually reduce peak tab temperature and total time at high voltage — the two biggest aging factors. Most capacity fade still comes from staying at 100% SOC in heat, not the charge rate itself.

Related reads: Our deep dive on satellite 5G power co-design and the on-device AI thermal budget explain why charging and compute can’t be designed in isolation.

References & Standards: Bluetooth SIG · GSMA Intelligence