How to Read a Mobile SoC Die Shot: Component Identification Guide

A die shot is the ground truth of a mobile SoC. Packaging and marketing slides can hide floorplan compromises, but silicon never lies. If you can read the texture, symmetry, and SRAM patterns on a die photo, you can reverse-engineer performance priorities, thermal bottlenecks, and cost trade-offs in minutes.

Modern flagship SoCs pack 12 to 20 billion transistors into ~110 mm². At that density, every square millimeter is contested. This guide gives you a systematic method to identify the major blocks — CPU cluster, GPU, NPU, ISP, memory system, and I/O — without delayering the chip.

1. How a Die Shot Is Made

Most public die shots are top-down optical photos after package decap and die polish. The die is chemically etched to remove passivation and sometimes several metal layers, then illuminated with coaxial or angled light. Contrast comes from reflectivity differences: dense logic appears mottled mid-gray, SRAM is highly uniform and bright, and analog areas look chaotic with curved metal.

Infrared (IR) backside shots see through the silicon substrate and emphasize the transistor layer. They are excellent for cache detection but obscure upper metal NoC routing. Front-side visible-light shots after etch show Metal 3-5 interconnect and are better for identifying bus widths and PHYs. Always check the caption for prep method — the same block can look inverted between IR and front-side imaging.

2. The Floorplan Logic: Where to Look First

SoC architects place blocks to minimize power delivery droop and thermal coupling. That creates predictable geography:

• Center and top-center: CPU cluster and large system-level cache (SLC). Needs lowest IR drop, so near power bumps.
• One large corner: GPU. Kept together for wide, low-latency interconnect to SLC and DRAM fabric.
• Edge ring: PHYs — LPDDR5/5X, UFS, PCIe, DisplayPort, USB. Recognizable as long, narrow strips with repeating bump pads.
• Opposite edge from modem: NPU/ISP/DSP row. Kept near memory controller but isolated from CPU thermal hot spot.

Start by outlining the die edge and counting the LPDDR PHYs. On recent Snapdragon, Dimensity and Tensor parts you'll find four 16-bit or two 32-bit LPDDR channels along one long edge. Those are your anchor.

3. Block-by-Block Visual Signatures

CPU Cluster: Heterogeneous but Ordered

Look for 1+3+4 or 1+5+2 core grouping near the center. Prime cores are visibly larger — about 1.6x the area of a performance core on the same node — with a distinct L2 island (bright, rectangular SRAM) attached to each core. Efficiency cores are tightly packed in a quad with a shared L2. Between cores you'll see a thin, dense strip: the core-to-core snoop interconnect.

Above or below the cores sits a large, very uniform rectangle: the shared L3 or system-level cache. It looks almost like a flat, light-gray tile because SRAM bitcells are perfectly repetitive. If you see a 4-6 mm² slab of uniform SRAM adjacent to the CPU, that's SLC. Its size correlates directly with gaming and multitasking performance.

GPU: The Tiled Monolith

The GPU is usually the single largest block, 18-28% of die area on flagships. Its texture is unmistakable: a grid of identical tiles repeating 6-12 times. Each tile contains ALUs, register files and a small local cache. The repetition creates a checkerboard effect under magnification. For deeper comparison of architectures, our mobile GPU architecture comparison breaks down how Adreno, Mali and Apple GPU tiling differs — a useful companion when you try to count shader cores from a shot.

Adreno and Apple GPUs tend to show very clean tiling with minimal control logic visible. Mali/Immortalis parts often have a slightly more heterogeneous periphery where the job manager sits. If a large block shows no obvious tiling and looks grainy, it's probably not GPU — it's DSP or modem.

NPU, ISP and Media Engine

The NPU sits close to the SLC but away from the CPU heat plume, often on the left edge in recent Qualcomm and MediaTek layouts. It has the densest, most regular pattern after SRAM — a systolic array of multiply-accumulate units. It looks darker and more finely grained than CPU logic, with narrow SRAM strips interleaved between compute columns.

The ISP and video codec block is messier: a mix of medium-grain logic, line-buffer SRAMs (long, thin bright bars), and MIPI CSI logic near the die edge. You will not see perfect tiling. If you spot many parallel 1-2 KB SRAM strips, that's the image line buffer — a dead giveaway for ISP.

Memory System, NoC and SLC

The network-on-chip fabric rarely photographs as a block at all; it's the mid-gray mesh routing between cores, GPU, and controllers. Its presence is inferred from wide metal busses crossing the die. The best marker is the LPDDR PHY: four identical, highly structured macros along one edge, each ~2.5 x 0.6 mm, with a repeating bump array and dense analog capacitor patterns.

System-level cache is the unsung area hero, often 6-8 mm² on 2025 flagships. Because it is rarely marketed, die shots are the only way to verify if a vendor actually increased cache versus prior generation. Count the SRAM tile repetitions to estimate capacity: each 1 MB of SRAM is roughly 0.55 mm² on N4P-class nodes.

Modem, RF and Analog Edges

If the modem is integrated, it appears as a large, irregular logic block with embedded SRAM and often a dedicated SRAM bank for L2. On parts with external modem, that area becomes additional CPU or NPU real estate — a quick way to distinguish integrated vs. discrete strategies. The die edge itself contains dozens of tiny, rectangular PHY blocks with pronounced guard rings. These are easy to confuse with logic after heavy etching, but their location on the scribe seal ring is definitive.

For RF-aware analysis, note that reconfigurable intelligent surfaces for 5G and on-die RF front-end integration are pushing modem-adjacent blocks to the periphery for isolation — you'll see larger keep-out zones (empty silicon) near those PHYs than around digital logic.

4. From Pixels to Millimeters: Quantitative

A die shot lets you estimate block area and transistor density without a spreadsheet. The workflow we use at Jones Consortium:

1. Correct perspective distortion, then measure die width in pixels between scribe lines.
2. Use vendor-disclosed die size (e.g., 113.5 mm²) or package ball pitch to derive mm per pixel.
3. Polygon-trace each block, compute pixel area, convert to mm² and percent of die.
4. Cross-check: SLC area / 0.55 ≈ SRAM MB on N4-class; GPU area scales linearly with shader core count.

A minimal script speeds this up when you have pixel polygons:

# estimate block area from die shot pixels
die_pixels = 4120 * 3850  # measured die bounding box
die_area_mm2 = 113.5      # vendor or TechInsights figure
mm2_per_px = die_area_mm2 / die_pixels

blocks = {# traced polygons in pixels
  "GPU": 2_810_000,
  "CPU_cluster": 1_420_000,
  "SLC_8MB": 1_050_000,
  "NPU": 620_000,
}
for name, px in blocks.items():
    print(f"{name:12} {px*mm2_per_px:5.2f} mm²  {px/die_pixels*100:4.1f}%")

# Validate SLC: ~0.55 mm² per MB on N4P -> 1_050_000*mm2_per_px ≈ 7.5 MB physical incl. ECC

Run this across generations to see strategy shifts. If a vendor claims “30% faster GPU” but die shot shows only +8% GPU area on the same node, the gain is mostly frequency and architecture, not scale — expect tighter thermal throttling. Pair this with protocol-level analysis such as mobile traffic optimization with QUIC and HTTP/3 when you want to connect silicon choices to real-world app latency.

5. Common Pitfalls and How to Avoid Them

1. Mistaking SLC for GPU cache. The GPU has its own L2 inside the tiled block. The large uniform slab between CPU and NoC is system cache, not GPU-private. Check adjacency: if it touches CPU L3 directly, it's SLC.

2. Over-counting NPU. The area shading you trace as “NPU” often includes the shared DMA and SRAM controller. True MAC array is 50-60% of that polygon. Report both total and compute-only.

3. Ignoring empty silicon. White or dark empty channels are not wasted — they are thermal and IR-drop keep-outs, or reserved for higher-bin SKU fusing. Don't include them in block area.

4. Process illusion. A block shrinks ~15% from N5 to N3 without changing function. Normalize area by node before comparing vendors. A 6 mm² NPU on N3B holds more compute than 7.5 mm² on N4P.

Looking ahead, 3D stacking and backside power delivery will change die-shot grammar again. With buried power rails, the metal texture shifts and blocks look flatter. Early research on angstrom-era nodes and terahertz interconnects, as surveyed in our mobile 6G terahertz research, suggests future floorplans may split logic and SRAM onto separate tiers — at which point a single top-down shot will no longer tell the full story.

The skill is to read intention, not just labels. When you can spot a vendor spending 2 mm² extra on SLC instead of another GPU core, you understand they are betting on system responsiveness and cache hit rate over peak FLOPS. That tells you more about next year's phone than any spec sheet.