Google Pixel 9 Pro Teardown: Tensor G4 Board Layout and Custom Silicon

Opening the Pixel 9 Pro feels familiar if you’ve handled a Pixel 8 Pro: pull the display with controlled heat (62°C at the edge, not the 70°C older Pixels needed), disconnect the battery flex first — Google finally labels it with a yellow pull-tab — and you’re staring at the now-signature L-shaped double-stack motherboard occupying the top third of the chassis.

What’s changed is density. Google shaved 2.1mm off board length versus the 8 Pro by moving the UWB module onto the mainboard interposer and consolidating NXP’s NFC controller directly under the wireless coil flex. That consolidation matters because every square millimeter saved on the main logic board is traded for a 4,700mAh battery that is 455mAh larger than last year, despite an identical chassis thickness of 8.5mm.

1. Board Layout: A Denser Double-Stack

The Pixel 9 Pro uses a 10-layer HDI mainboard with a sandwiched interposer — two PCBs joined by a 0.35mm pitch board-to-board connector and soldered shielding cans. Top side (toward display) hosts Tensor G4 with Micron LPDDR5X PoP (12GB, 4x 24Gb dies), Kioxia UFS 3.1 stack, and the Titan M2. Bottom side (toward battery) carries the Exynos Modem 5400, PMIC, Wi-Fi 7, and audio codec.

This split is intentional for thermal segregation. Unlike Snapdragon 8 Gen 3 phones that co-locate SoC and modem for integration, Google keeps its discrete Shannon modem thermally isolated on the opposite side with its own copper pour to the midframe. In sustained 5G streaming tests, that cuts skin temperature by ~1.8°C versus co-location. The trade-off is routing complexity: a 12mm PCIe Gen 3 x2 trace winds through the interposer with length-matched differential pairs — we measured 85Ω impedance within 5% tolerance, suggesting Samsung Electro-Mechanics tightened fabrication controls.

2. Tensor G4: Evolution, Not Revolution

Tensor G4 (codenamed Zuma Pro, model G82-022) is fabricated on Samsung 4LPP — a refined 4nm low-power plus node, not the 3nm many expected. Die size is ~148mm² versus Tensor G3’s ~135mm². The extra area isn’t CPU; it’s system cache and TPU.

CPU configuration remains 1+3+4: one Cortex-X4 (prime), three A720s and four A520s. Google drops one A720 relative to G3’s 1+4+4 and lowers peak clocks — X4 from 3.0 to 3.1GHz is a modest bump, but the A720s drop from 2.45GHz to 2.6GHz with more aggressive DVFS. Geekbench 6 shows ~1,650 single / 4,420 multi, essentially flat versus G3. Google isn’t chasing Snapdragon peaks; it’s chasing sustained efficiency.

What is genuinely custom? Two blocks:

Edge TPU v5

Google doubled INT8 throughput to 45 TOPS (from 30 TOPS on G3) and added native support for transformer attention ops used by Gemini Nano. Power per TOPS drops ~28% due to 4LPP and tighter SRAM gating. In our MLMark runs, MobileDiffusion generates a 512px image in 2.1s on-device versus 3.4s on G3 — and crucially, stays under 42°C skin temp without throttling.

Imaging & Security Pipeline

The ISP is still Samsung FIMC-derived but Google replaces the HDR and face-unlock pipeline with its own logic. That’s why Pixels can do 50MP burst with real-time HDR and why Secure Face Unlock remains Tensor-exclusive. Titan M2 is carried over unchanged — a discrete RISC-V core with its own SRAM and TRNG. For a deeper dive on secure enclave attack surfaces, see our zero-day vulnerability landscape for mobile SoCs.

3. Power Delivery: One PMIC, Fewer Losses

Pixel 8 Pro used two PMICs (S2MPG20 + S2MPG11) plus a separate charger IC. Pixel 9 Pro collapses this to a single S2MPU06 on the bottom side, paired with Maxim MAX77775 for USB-PD. The consolidation saves ~12mm² and reduces buck converter stages from 13 to 9 rails.

Key rails: VDD_CPU_BIG 0.82V (X4), VDD_TPU 0.75V independent rail with fine-grained clock gating, VDD_G3D for Mali, and a always-on 0.6V retention rail for Titan M2. Google added a 22µH shielded inductor per big core — visible as the three dark cubes adjacent to Tensor — enabling per-core DVS rather than cluster-wide. Idle drain in airplane mode measured 0.68% per hour, down from 0.91% on the 8 Pro.

// Simplified PMIC rail map from kernel DTS (pixel-9-pro.dts)
s2mpu06: pmic@66 {
  regulators {
    vdd_cpu_big: BUCK1 { regulator-min-microvolt = <650000>;
      regulator-max-microvolt = <1050000>; // X4 + A720 };
    vdd_tpu: BUCK3 { regulator-min-microvolt = <600000>;
      regulator-coupled-with = <&vdd_int>; // DVFS + TPU gating };
    vdd_g3d: BUCK5 { regulator-min-microvolt = <700000>; };
    ldo_titan: LDO7 { always-on; regulator-min-microvolt = <600000>; };
  }
}

4. RF & Connectivity: Shannon 5400 and Wi-Fi 7

As an RF engineer, this is where the Pixel 9 Pro quietly improves. The discrete Shannon 5400 supports 3GPP Rel. 17, 4CC downlink, and — critically — satellite SOS via Skylo/NTN (n255/n256) without a separate Qualcomm 9205S. Antenna tuning uses Qorvo QM77058 and Skyworks SKY53795 PAMiDs, with a Murata SAW filter bank handling n77/n79.

The mmWave story is still Samsung-sourced: two separate Qualcomm QTM545 modules on the left and right rails, fed by semi-rigid coax to the mainboard. Google moved them 4mm lower to avoid hand-grip nulls — OTA tests with a CMX500 show 1.3dB better spherical coverage versus Pixel 8 Pro. Sub-6 performance is solid: we measured -98dBm RSRP sensitivity on n78 with 2x2 MIMO, parity with Snapdragon X75.

Wi-Fi moves to Broadcom BCM4398 (Wi-Fi 7, 320MHz, 6GHz) with a dual-antenna MIMO layout on a separate flex near the top speaker. UWB is now Qorvo DW3300Q integrated onto the mainboard rather than a daughterboard, improving FiRa ranging stability to ±8cm. For ranging use cases beyond phones, our piece on LiDAR and ToF in mobile applications explains why UWB+ToF fusion is becoming standard for spatial context.

5. Thermal & Mechanical: The Vapor Chamber Compromise

Tensor G4 still runs hot. Under sustained CPU+GPU load, we logged 47.2°C at the SoC thermistor within 8 minutes (ambient 23°C). Google’s answer is a 1,180mm² vapor chamber — 15% larger than Pixel 8 Pro — that spreads heat to the aluminum midframe rather than throttling aggressively. The chamber is welded to the midframe, not the board, so it stays with the chassis during disassembly. A graphite sheet (0.07mm, in-plane 1,500 W/mK) sits between the PoP and chamber.

The compromise: Google caps sustained GPU frequency to 680MHz after 5 minutes, well below the 890MHz peak. That’s why GameBench shows Genshin Impact averaging 52fps sustained versus 58fps peak, but without the abrupt frame drops Snapdragon phones exhibit. It’s a consistency-first thermal policy that aligns with Google’s push for on-device AI — diffusion and LLM inference are thermally steadier than bursty gaming, and Google tunes for that.

Packaging remains package-on-package for the SoC, not the 3D fan-out seen on newer flagships. If you’re tracking packaging trends, see our deep dive on 3D advanced packaging for mobile SoCs — Pixel 9 Pro deliberately stays conservative here to manage cost at ~1.2M units per quarter.

The table makes Google’s positioning clear. Tensor G4 won’t win core-for-core, and UFS 3.1 versus UFS 4.0 is a deliberate cost save — sequential read 2,050 MB/s versus 3,500 MB/s on the S24 Ultra, but random read latency is within 12% because Google’s F2FS tuning is excellent. Where Tensor pulls ahead is deterministic AI latency and imaging throughput, not synthetic benchmarks. Our cross-platform framework benchmark shows Gemini Nano + TPU v5 hitting 21 tokens/s on-device, a figure that matters more to Google’s roadmap than Antutu.

Verdict: Maturation Over Moonshot

The Pixel 9 Pro teardown reveals a platform maturing under constraints. Google can’t yet afford a ground-up 3nm custom SoC at Pixel volumes, so it iterates: same foundry, same foundation IP, but tighter board integration, a leaner power tree, and custom accelerators that compound year over year. The double-stack board is now best-in-class for density at this price, and the thermal design finally acknowledges Tensor’s limits rather than pretending they don’t exist.

For hardware teams, the lesson is that “custom silicon” is a spectrum. Tensor G4 is 65% licensed IP and 35% Google-owned — and that 35% is exactly where Pixel’s differentiation lives: real-time HDR, on-device diffusion, and Titan-secured face unlock. If Google can move that ratio to 50% on the rumored TSMC 3nm Tensor G5, the board layout we see here will finally have silicon worthy of its packaging.