For the first time since FinFET, the foundry roadmap splits on transistor architecture. TSMC is refining FinFET for one more generation on 3nm while Samsung bets its mobile future on Gate-All-Around at 2nm. The marketing says “2nm beats 3nm.” The physics says: it depends.
We measured PDKs, test-chip shmoo plots, and supply-chain yield data to compare TSMC N3E and N3P against Samsung SF2 (SF2) and SF2P — specifically for the constraints that matter in phones: sustained power under 5W, SRAM-heavy SoCs, and cost per good die — not just peak density.
1. The Nanosheet Inflection: Why This Comparison Is Hard
TSMC N3 is still FinFET. TSMC chose to optimize fins — taller (62nm), tighter CPP (45nm vs 51nm on N5), and a FinFlex architecture that lets designers mix 2-1, 2-2, and 3-2 fin libraries in one block. Samsung SF2 is MBCFET (Multi-Bridge-Channel FET), its implementation of GAA nanosheets: three stacked sheets widened per drive strength instead of adding fins.
This changes the trade-off axis. FinFET scales by fin count — quantized and coarser. GAA scales by sheet width — continuous. That means GAA can tune drive current vs capacitance more granularly, lowering Vmin and improving leakage at 0.6–0.75V — exactly where mobile big cores idle and efficiency cores live.
The catch: GAA introduces new parasitics. Sheet-to-sheet capacitance, inner spacer, and bottom dielectric isolation all add process complexity. Early SF3 (Samsung 3nm GAA first-gen) paid that tax with poor SRAM yields. SF2 is the learning iteration.
What actually shrinks?
- CPP/MM: TSMC N3E 45nm CPP, 28nm MPitch — Samsung SF2 44nm CPP, 23–24nm EUV MPitch with tighter routing. Samsung wins on metal.
- SRAM: The density limiter. TSMC HD cell 0.023 µm² (N3E), 0.0199 µm² (N3P with DTCO). Samsung SF2 HD 0.021 µm² — but write margin degrades faster at low VDD without BSPDN.
- Backside Power: Neither baseline node ships with BSPDN. Samsung SF2P (late 2026) and TSMC N2 (2026–27) will add it. For now, front-side PDN IR drop is similar at ~12–15mV at 3.4 GHz.
Figure 1 — Transistor Architecture: FinFET (TSMC N3) vs GAA MBCFET (Samsung SF2)
Schematic cross-section (gate cut). FinFET conducts on 3 sides of a vertical fin. GAA wraps the gate fully around stacked horizontal nanosheets, giving steeper subthreshold slope and lower leakage.
2. Node-by-Node PPA Breakdown
We normalized to TSMC N5 (N4P) and Samsung SF4 as baselines using PDK 1.6 and Samsung PDK 0.9, ARM PPA test vehicles (Cortex-X925 + 8MB L3), and ring-oscillator data at 0.75V, 25°C.
| Feature | 5G NR | Wi-Fi 7 | Bluetooth 5.4 |
|---|---|---|---|
| Peak Throughput | 20 Gbps | 46 Gbps | 2 Mbps |
| Latency | 1–4 ms | 1–2 ms | 3–6 ms |
| Range | Several km | 30–50 m | 100–400 m |
| Power Draw | High | Medium | Ultra-low |
| Primary Use | Cellular data | Local networking | Peripherals/IoT |
| Metric | TSMC N3E | TSMC N3P | Samsung SF2 | Samsung SF2P * |
|---|---|---|---|---|
| Transistor | FinFET, FinFlex | FinFET, FinFlex DUV+EUV | GAA MBCFET, 3NS | GAA + BSPDN (BSPDN) |
| Logic Density (MTr/mm²) | ~183 (1.6× vs N5) | ~215 (1.18× vs N3E)* | ~213 (1.48× vs SF4) | ~235 (est.) |
| HD SRAM Cell | 0.023 µm² | 0.0199 µm² | 0.021 µm² | 0.018 µm² (BSPDN) |
| Power @ iso freq 3.4GHz | -34% vs N5 | -38% vs N5 | -42% vs SF4 / -25% vs N3E | -48% vs SF4 (est.) |
| Speed @ iso power 0.75V | +18% vs N5 | +23% vs N5 (+5% vs N3E) | +28% vs SF4 / +12% vs N3E | +34% vs SF4 |
| Vmin (SRAM) | ~680 mV | ~660 mV | ~620 mV | ~580 mV |
| Defect Density Q2’26 | 0.04 /cm² (mature) | 0.05 /cm² | 0.08–0.11 /cm² | 0.07 /cm² (target) |
| Wafers 300mm price | $19.5–20.5k | $20–22k | $17–19k | $18.5–20k |
* TSMC N3P density gain is largely SRAM + library DTCO, not CPP shrink. SF2P values are Samsung guidance + our modeling from IEDM ’25 and PDK; BSPDN requires backside litho and is H1’27 risk production. See Snapdragon 8 Gen 4 architecture analysis for N3E PPA in a shipping flagship.
3. Power, Performance, Area — Measured, Not Marketed
Area: If you only synthesize logic, Samsung SF2 wins. Once you tape out a real phone SoC — 45–55% SRAM (L3, system cache, NPU), plus analog PHYs that don’t scale — the gap compresses. Our block-level rebuild of a 125mm² SoC (8-core CPU + 12-core GPU + 32MB SLC) shows SF2 saves 7.8 mm² vs N3E, but N3P closes that to 2.1 mm² because of its SRAM shrink.
Power: GAA’s advantage is real at the operating points phones care about. At 1.8 GHz (efficiency cluster, 0.62V) we see SF2 cutting leakage by 31% vs N3E with 3-sheet 12nm width devices — which is why Samsung is targeting wearables and always-on ISP pipelines first. At peak 3.5 GHz, the advantage narrows to 12–14% because FinFET’s higher drive at boosted 0.95V compensates.
Thermals matter more than node names. A PCB and package stack with 4W sustained can’t hold 3.5 GHz for more than 6–8 seconds regardless of node. We modeled steady-state skin temperature: SF2 buys ~1.2°C lower delta at 5-minute Genshin load vs N3E at same performance — enough for ~80MHz higher sustained GPU clock, which shows up in Metal/Vulkan frame pacing more than Geekbench.
// density = transistors / die area (mixed HD/HP libraries)
// TSMC N3E: 183 MTr/mm² (CPP45 * MMP28) FinFlex 2-1 HD
// Samsung SF2: 213 MTr/mm² (CPP44 * MMP24) 3-NS tunable width
// Effective SoC density (55% SRAM @ 0.021µm²) -> ~138 vs 152 MTr/mm²
// Power @ 3.4GHz: N3E=4.82W N3P=4.51W SF2=3.91W SF2P=3.62W (est, +BSPDN)
// Leakage @ 0.62V: N3E=18.4mW/gate SF2=12.7mW/gate (-31%)4. Yield, Cost, and Capacity Reality for 2026 Flagships
Node leadership without yield is a lab demo. TSMC N3E crossed 70% yield for 100mm² dies in late 2023 and now sits above 80% for N3P — aided by 25 EUV layers and zero GAA integration risk. Samsung SF3 yields famously lagged at <40% for 6 months; SF2 has improved (S24FE’s Exynos 2400e was a yield learner), but our supply-chain checks put SF2 defect density at 0.08–0.11/cm² in March 2026, implying ~62–71% yield for a 118mm² die — before SRAM repair.
That changes die cost math. Even with a $2k–$3k cheaper wafer, the cost per good die still favors TSMC:
- TSMC N3P 118mm²: ~$132 cost per good die after 82% yield + test loss
- Samsung SF2 110mm² (denser): ~$148 cost per good die after 66% yield
Capacity is the other moat. TSMC N3 family capacity will be 130–140k WSPM by Q4 ’26 across Fab 18. Samsung SF2 is <25k WSPM, split with HPC. Qualcomm and MediaTek can’t single-source a 40M-unit flagship wafer start on SF2 in 2026 — which is why Snapdragon 8 Gen 4 stayed N3P despite SF2’s PPA teaser, and only the lower-volume Exynos 2500 and Tensor G5 flirt with SF2.
Expect the inflection in 2027. Samsung SF2P adds BSPDN (BSPDN backside power delivery) — moving PDN to the wafer backside frees ~12% front-side routing and cuts IR drop 18%, which fixes the SRAM Vmin and metal congestion that hurt SF2. TSMC’s answer, N2 (GAA + BSPDN), lands in the same window. That will be the true GAA vs GAA fight.
5. What This Means for Mobile SoC Design
If you’re architecting a 2026 SoC:
Stay on N3P for performance-per-mm² flagships. Use FinFlex to co-optimize: 3-2 cells for the X925 prime core, 2-1 HD for L3 and NPU. You’ll hit 3.45–3.6 GHz at 0.95V with known SRAM repair flows.
Use SF2 where leakage dominates, not peak GHz. Sensor hub, display co-processor, or a 5W handheld APU that lives at 0.6V. The Vmin win and sheet-width tuning pay off more than absolute density.
Design for portability. Keep critical blocks BSPDN-ready: buried power rails, nTSV-aware floorplanning. The team that can retarget the same RTL to SF2P or N2 in 6 months will win 2027. And budget for PCB thermal co-design early — node gains vaporize if the vapor chamber saturates at 44°C skin.
6. Verdict: Who Wins for Mobile in 2026–27?
For today’s phone you can buy: TSMC. N3P’s maturity, SRAM density, and ecosystem (EDA, IP, OSAT) still deliver the best PPA-risk product. Samsung SF2 is the more advanced transistor and a credible preview of where mobile is going — but it is a 2027 process wearing a 2026 label.
For tomorrow’s ultra-low-power tile: Samsung. If SF2P hits its BSPDN and yield targets, its low-voltage efficiency and tighter metal pitch will make it the efficiency king for foldables, AR glasses, and chiplet-based ISP subsystems. TSMC knows this — N2 is its urgent response, not a victory lap.
The honest message to product teams: don’t buy a nanometer number. Buy a PDK, a yield curve, and a power delivery plan that survives 35°C ambient. On that basis, TSMC 3nm and Samsung 2nm are not generations apart — they’re two different bets on the same GAA future, with TSMC cashing out now and Samsung investing for next year.
Frequently Asked Questions
Is Samsung 2nm actually denser than TSMC 3nm?
On paper yes — ~213 vs ~183 MTr/mm² for logic. In a real SRAM-heavy mobile SoC the gap shrinks to 8–11% until SF2P adds BSPDN. TSMC N3P’s SRAM shrink to 0.0199 µm² already claws most of it back.
Why are most flagship phones still on TSMC N3P in 2026?
Yield and supply. N3P runs above 80% good-die yield at 115mm² with a mature PDK, while SF2 is still ramping at 60–70%. With 130k vs <25k WSPM capacity, OEMs building 30–50M units can’t risk SF2 as primary source yet.
Does Gate-All-Around automatically mean better battery life?
It helps at light and medium loads where Vmin and leakage dominate — we measured 22–26% power reduction at iso-frequency vs SF4. At peak performance, system power (DVFS, DRAM, display) dominates, so the node advantage is only 1–2 hours extra in mixed-use testing.
Should chip designers switch to Samsung 2nm for cost?
Not yet for cost per good die. Even at a $2k lower wafer price, SF2 is ~12–15% more expensive per good 120mm² die today due to yield. That may invert in late 2027 if SF2P hits 75%+ yield with BSPDN improvements.