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On-Device LLM: Running Large Language Models on Mobile Hardware

Cloud LLMs are powerful but slow, expensive and private-data hostile. The next frontier is running 2–7B parameter models directly on the NPU — with sub-300ms latency, offline execution, and no data leaving the device.

Marcus Chen, Mobile Hardware Analyst September 21, 2026 8 min read Updated for Android 15 & iOS 18 NPU runtimes

For three years, mobile AI meant sending a prompt to the cloud. That model is breaking. With Gemini Nano, Apple Intelligence, and Snapdragon’s on-device Llama, flagship SoCs now execute generative AI entirely within the memory and power envelope of a phone — typically under 4W sustained and 6GB of available DRAM.

This shift is not just software. It’s a hardware-software co-design problem that touches quantization, KV-cache management, heterogeneous compute scheduling, and thermal budgeting. Understanding it is essential for anyone building AI-first mobile experiences.

1. Why On-Device? The Physics of Cloud Inference

Cloud inference has three structural liabilities on mobile:

  • Latency: Round-trip 4G/5G adds 80–350ms even before model compute. On-device decode can deliver first token in 180–250ms.
  • Privacy & compliance: Health, messaging and enterprise data cannot leave the device in many jurisdictions. On-device keeps embeddings local.
  • Availability & cost: Offline mode is mandatory for automotive and field use, and per-token cloud pricing scales poorly at millions of devices.

The tradeoff is capability. You cannot fit GPT-4 (1T+ parameters) on a phone. On-device LLMs target assistive tasks — summarization, smart reply, grammar, entity extraction, and tool-use — where a 1.8B–3.8B model fine-tuned for the task outperforms a distant giant.

Design principle: On-device LLMs are not smaller ChatGPTs. They are domain-specific accelerators, like an ISP is to a camera — optimized for latency and power, not generality.

2. The Hardware Stack: NPU, Memory, and the Bottleneck

Modern mobile SoCs, from Google’s Tensor G4 detailed in our Pixel 9 Pro teardown to Snapdragon 8 Gen 3, share a similar hierarchy:

Mobile Connectivity Standards Comparison
Feature 5G NR Wi-Fi 7 Bluetooth 5.4
Peak Throughput20 Gbps46 Gbps2 Mbps
Latency1–4 ms1–2 ms3–6 ms
RangeSeveral km30–50 m100–400 m
Power DrawHighMediumUltra-low
Primary UseCellular dataLocal networkingPeripherals/IoT
On-Device LLM Inference — SoC Block Diagram Architecture showing LLM prompt flow through CPU, NPU, SRAM and LPDDR5 with prefill and decode phases. MOBILE SOC — LLM INFERENCE PIPELINE CPU Cluster Tokenizer • Orchestration NPU / AI Accelerator INT4/INT8 Systolic Array • 35-45 TOPS GPU Fallback • Dequant • Attention DSP / HVX Audio • Pre/Post proc On-Chip SRAM / Cache (4-12 MB) Weights tiles • KV-Cache hot set • Ultra-low latency LPDDR5 / LPDDR5X (12-16 GB) Quantized model (~1.5-3.5 GB) • KV-Cache cold Bandwidth 51-77 GB/s — PRIMARY BOTTLENECK DMA Tiles PREFILL (Compute-bound) Parallel prompt processing • High TOPS utilization ~600-1200 tok/s on Snapdragon 8 Gen 3 DECODE (Memory-bound) Autoregressive • 1 token at a time • KV-cache streaming ~12-35 tok/s — limited by DRAM bandwidth
Figure 1 — LLM inference on a mobile SoC splits into two phases: compute-bound prefill and memory-bound decode. NPU SRAM locality is critical for decode throughput.

Key insight: TOPS is misleading. Prefill scales with TOPS, but decode — where the user waits for streamed tokens — is bound by how fast you can move weights and KV-cache from DRAM into the NPU. This is why unified memory architecture and larger system-level cache, as seen in newer chiplet architectures for mobile SoCs, matter more than headline NPU numbers.

3. Making Models Fit: Quantization, Distillation & KV-Cache

A 3B model at FP16 needs 6 GB just for weights — impossible on a phone. Production on-device models rely on three techniques:

4-bit quantization (AWQ, GPTQ, QLoRA)

Weights are compressed to INT4 with per-group scaling (group size 128). Activation stays INT8/FP16. A 3.8B Phi-3 Mini drops from 7.6 GB (FP16) to ~2.1 GB (INT4 + overhead) with <2% accuracy loss on summarization. NPUs now have native INT4 datapaths to avoid dequantization on the fly.

Knowledge distillation & pruning

Gemini Nano (1.8B / 3.25B variants) is distilled from Gemini Pro with instruction tuning for on-device domains. Structured pruning removes 15–25% of attention heads while keeping latency stable.

KV-cache optimization

The KV-cache grows linearly with context length: 2 × layers × dim × tokens × bytes. At 4K context, a 3B model cache can exceed 600 MB. Techniques like PagedAttention, 8-bit KV quantization, and sliding-window attention (as in Gemma 2B) cut this by 50%.

# Quantize with llama.cpp — produce Q4_K_M for NPU runtime
./llama-quantize phi-3-mini-f16.gguf phi-3-mini-q4.gguf Q4_K_M

# ExecuTorch / QNN export for Snapdragon NPU (INT4 weights, INT8 act)
import torch
from executorch import exir
model = exir.capture(model).to_edge()
 quantized = exir.quantize(model, "qnn-8a4w") # 8-bit act, 4-bit weight
exir.save(quantized, "model.pte")

4. Platform Comparison: How the Vendors Do It

PlatformModel ExampleNPU / TOPSPrecisionMemoryMeasured Speed
Google Tensor G4 + AICoreGemini Nano 1.8B / 3.25BEdge TPU • ~45 TOPSINT4 weight, INT8 KV12 GB LPDDR5X~14 tok/s decode (Nano 1.8B)
Snapdragon 8 Gen 3 (Hexagon NPU)Llama 3.2 3B, Phi-3 MiniHexagon • 45 TOPS (INT8)INT4/INT8, 8a4w77 GB/s LPDDR5X22–30 tok/s decode (Q4)
Dimensity 9300+ (APU 790)Llama 3 3B, Gemma 2BAPU • 48 TOPSINT4 mixedUp to 9600 Mbps~20 tok/s decode
Apple A17 Pro (Neural Engine)Apple Foundation 3B (on-device)16-core ANE • 35 TOPSINT8 / FP168 GB Unified, 51 GB/s~18 tok/s decode*

* Apple offloads larger models to Private Cloud Compute; on-device model is limited to ~3B via Core ML + ANE. Speeds are Q4 quantized, averaged across 512-token context, batch size 1.

Qualcomm’s QNN and MediaTek’s NeuroPilot push quantization-aware execution closest to the metal, while Google’s AICore abstracts Gemini Nano behind a system-level API with LoRA adapter support — allowing apps to fine-tune without shipping a full model. For power budgeting, the same thermal constraints that affect wireless charging coil design — skin temperature limits of 43–45°C — cap sustained NPU power to ~3.5W, throttling decode speed after ~20 seconds.

5. The Software Runtime: Where Fragmentation Lives

Hardware is only half the battle. The runtime determines if your model runs at all:

  • Android: NNAPI is deprecated; AICore (Gemini Nano), QNN (Snapdragon), and MLC-LLM / llama.cpp (GPU via OpenCL/Vulkan) compete. ExecuTorch is emerging as a unified path.
  • iOS: Core ML + MLX + ANE via MIL. Apple requires model conversion to Core ML format and enforces strict memory limits (~50% of RAM per app).
  • Cross-platform: ONNX Runtime, MNN, and TFLite still used for smaller SLMs, but lack advanced KV-cache paging.
// Android AICore — Gemini Nano system service (API level 34+)
val model = GenerativeModel.aicore()
val response = model.generateContent("Summarize this email: ...")
// Runs on Edge TPU, no network, LoRA adapters auto-mixed

// llama.cpp on-device via GPU delegate (fallback)
./llama-cli -m phi-3-q4.gguf -p "Rewrite:" --threads 6 --gpu-layers 28

Security is non-trivial: prompt injection and weight tampering are new attack surfaces. This is why vendors isolate model weights in TEE and enforce mobile kernel exploit mitigations around the NPU driver — a compromised NPU DMA can read app memory.

6. Practical Limits & What’s Next

Today’s ceiling: 2K–4K context is practical; 8K is possible with sliding window but increases KV pressure. Multi-turn chat sustains ~15 tok/s on flagship, dropping to 6–8 tok/s on mid-tier (Snapdragon 7+ Gen 3). Power draw during decode is 2.8–4.2W — about 60% of peak gaming.

Next 18 months:

  • Mixture-of-Experts (MoE) for mobile: 7B MoE with 2 active experts gives 1.5B active compute with 7B knowledge, ideal for heterogeneous NPUs.
  • Speculative decoding: A tiny 0.5B draft model proposes 3 tokens, the main model verifies in one pass — 1.8× speedup in decode.
  • Unified memory & LLC: Chiplet SoCs with 16–24 MB system cache will halve DRAM traffic, directly improving tokens/second.
  • On-device RAG: Vector DB + embeddings stored on-device (via SQLite + NPU embedding model) to ground the SLM without the cloud.
Bottom line for builders: Design for 3B INT4, 2K context, and ~20 tok/s. If your UX needs longer context or faster generation, architect speculative or streaming UI (show partial tokens) rather than waiting for hardware.

On-device LLM is no longer research — it’s a hardware-guaranteed API. The winners will be apps that treat the NPU like the camera ISP: a constrained, always-available coprocessor that enables private, instant intelligence without a network round trip.

Frequently Asked Questions

How large is an on-device LLM compared to ChatGPT?

On-device models are 1–7B parameters versus 70B+ for cloud models. A 3B model quantized to 4-bit uses ~1.7 GB, fitting in mobile LPDDR5 and NPU SRAM, while cloud models require data-center GPUs with hundreds of GBs.

Why is NPU performance more important than CPU or GPU for LLMs?

LLM inference is dominated by matrix multiplications. NPUs use systolic arrays and native INT4/INT8 pipelines with large on-chip SRAM, delivering 10–20× better tokens-per-watt than general-purpose CPU/GPU cores.

Does on-device LLM work offline?

Yes. Once downloaded, the quantized model runs entirely locally via runtimes like AICore, Core ML, or QNN with no internet required. This enables sub-300ms response, airplane-mode use, and fully private processing.

What limits on-device LLM speed the most?

Memory bandwidth during the decode phase. Each generated token must stream weights and the growing KV-cache from DRAM. LPDDR5 bandwidth and thermal throttling—not raw TOPS—determine real-world tokens-per-second.

References & Standards: IEEE 802.11 · GSMA Intelligence